1. Field
Various embodiments described herein relate to a circuit module used to perform a scan test, a semiconductor integrated circuit, and an inspection apparatus used to inspect scan data and method of implementing same.
2. Description of the Related Art
Typically, as a means for achieving the low power consumption of a semiconductor integrated circuit, there has been known a technique to control a clock signal supplied to data-retaining elements constituting a sequential circuit, such as flip-flops and latches. The technique to control a clock signal is intended to, for example, stop the operation of each circuit module within the semiconductor integrated circuit for which data is not updated according to the operation thereof, by not supplying a clock signal to the circuit module. In the technique to control a clock signal, the clock signal is controlled by a clock gating circuit having at least a control signal and a clock signal as the inputs thereof. The control signal for controlling the supply of the clock signal is generated within the semiconductor integrated circuit.
For example, if the control signal input to the clock gating circuit permits a supply of the clock signal, then the clock gating circuit outputs the clock signal. In contrast, if the control signal does not permit a supply of the clock signal, then the clock gating circuit outputs data fixed to, for example, 0 or 1.
In addition, as a means for achieving the low power consumption of a semiconductor integrated circuit, there has been known a technique to control a power supply voltage (hereinafter referred to as power). The technique to control power is intended to, for example, stop the operation of a circuit module for which data is not updated according to the operation of the semiconductor integrated circuit, by not supplying power to the circuit module. In the technique to control power, power is controlled by a power gating circuit having at least a control signal and power as the inputs thereof. The control signal is generated by a control signal generation circuit within the semiconductor integrated circuit.
Furthermore, as a technique to make easy a test of a semiconductor integrated circuit, there has been a typical scan test. The scan test is a technique to control or observe the interior portion of a semiconductor integrated circuit using only a small number of I/O (Input/Output) terminals external to the semiconductor integrated circuit. In the scan test, data-retaining elements within the semiconductor integrated circuit are replaced with data-retaining elements for scan testing in order to constitute a shift register.
Next, in test mode, a shift register is formed by serially connecting data-retaining elements for scan testing. Thus, there is configured a scan chain whereby the data-retaining elements for scan testing may be controlled or observed from I/O terminals external to the semiconductor integrated circuit.
Still furthermore, as a means for reducing the scan test time of a semiconductor integrated circuit, there has been a typical technique to switch the output of each module including data-retaining elements constituting a scan chain, using a selection circuit (U.S. Pat. No. 2,676,169). A selection is made using the selection circuit, as to whether the output data of a shift register within the module in question is output to other circuit modules or a scan signal is output to other circuit modules without letting the scan signal go through the shift register.